Intel CEO: Lithography, Multi-patterning Delay 10nm (April 2018)


During Intel's Q1-2018 earnings conference call, CEO Brian Kraznich said, “Volume production (of 10nm) is moving from the second half of 2018 into 2019...We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify...They're really tied to this being the last technology tied to not having EUV and the amount of multi-patterning and the effects of that on defects...Think of them as improvements to the various edge stuff, the lithography stuff and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that.”

Sources: Transcript of Intel's Q2-2018 conference call on; EETimes coverage of the 10nm delay


Global Foundries: EUV “Not Ready Today” (January 2018)


Gary Patton, CTO & SVP of Worldwide R&D for GlobalFoundries, said 7nm will be in risk production at in 2018, and full production in 2019, using immersion lithography and quad patterning, but not EUV. The plan is to later offer a version of the 7nm process using the new EUV tools. EUV is “not ready today” Patton said, citing issues with source power, resist materials, and the masks, particularly with development of the proper pellicle (a thin film that goes over the mask or reticle.)
(source: PC Magazine, January 2018)

At the SPIE Advanced Lithography conference in February, 2018, George Gomba, Global Vice President of Technology Research at GlobalFoundries, said in a keynote address, “If we do not make productivity and availability improvements, we may only be able to use EUV for the most aggressive processors.”
(source: EETimes coverage of the 2018 SPIE Advanced Lithography conference)


IMEC: Higher Energy EUV Photons Increase Probabilty of Highly Unlikely Events (March 2018)


“In the EUV case, you have a much higher energy photon. it’s much more complicated and it’s really not well understood,” said Gregory McIntyre, director of the Advanced Patterning Department at Imec. “It creates high-energy electrons that quickly cascade into lower energy electrons. Those electrons then interact with whatever they happen to bump in to. With this, there are quite a few unknowns, such as how many electrons are being generated and what are the energies—and more importantly, what kind of chemistries are resulting because of those electrons.”

“As we go to smaller and smaller feature sizes, what we find is that the Gaussian distribution starts to grow a tail and become asymmetric on one side. This growth of the tail leads to the increasing probability of highly unlikely events,” McIntyre said.

Years ago, stochastics and shot noise were not on the radar screen, but the issues began to appear in 193nm lithography. In 193nm, chipmakers use a dose of 10mJ/cm² near the edge of a feature. “If I take a 1nm² area, then over the course of that exposure, 97 photons on average will pass through that area and go into the photoresist. But if I look at this larger volume of 10nm² on a side, I will have 9,700 photons on average,” explained Chris Mack, CTO of Fractilia. So, with an ample number of photons to process a feature, the photon shot noise or variation amounts to only 1%, according to Mack.

In contrast, EUV photons have 14 times more energy per photon than 193nm light. “That means for the same dose, EUV has 14 times fewer photons,” Mack said. “So while in the example above, we had 97 photons exposing a 1nm² area, at EUV there are only 7 photons. The relative uncertainty is 1/square root of the number of photons. For 97 photons, that is a +/- 10% uncertainty. For 7 photons the uncertainty is +/- 40%.

Source: EUV's New Problem Areas (Semiconductor Engineering, March 2018)